Digital circuitry is used in myriad applications which touch virtually every aspect of life. Consider, for example, the extensive use of digital data processing circuitry in data processing systems. Conventional digital circuitry is sometimes designed to permit functional and timing validation thereof.
FIG. 1 illustrates a conventional parallel signature analysis (PSA) circuit having a plurality of data inputs respectively connected to a plurality of nodes A, B . . . C within an operational digital circuit. The PSA circuit of FIG. 1 includes a plurality of master/slave type shift register latches (SRLs), each having a master latch stage (MLAT) and a slave latch stage (SLAT). As seen from FIG. 1, nodes A, B and C are sampled on the master clock LMT. Assuming that node A behaves in the manner illustrated by FIG. 2, then the fall and rise of node A will be completely missed (assuming for this example falling edge clocking of the latch) as illustrated by the sample of A in FIG. 2, sample points being designated by Xs. The illustrated transition of node A could be the expected and proper transition, an incorrect and invalid transition, or a spurious transition. Regardless of the nature of the illustrated transition, however, it cannot be properly captured by the conventional parallel signature analysis circuitry of FIG. 1.
It is there desirable to provide digital circuitry having a parallel signature analyzer that improves upon the aforementioned disadvantageous result obtained with the parallel signature analyzer of prior art FIG. 1.
The present invention provides digital circuitry having a parallel signature analyzer with a sampling feature that improves upon the results obtained with prior art FIG. 1.